1. Field of the Invention
The present invention relates generally to methods for forming trench fill layers within trenches within substrates employed in microelectronics fabrication. More particularly, the present invention relates to methods for forming gap filling trench fill layers within trenches within substrates employed in microelectronics fabrication.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes, and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
As integrated circuit device technology has advanced and integrated circuit device dimensions have decreased, it has become increasingly common within advanced integrated circuits to employ trench isolation methods such as shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods to form trench isolation regions nominally co-planar with adjoining active semiconductor regions of semiconductor substrates. Such trench isolation methods typically employ a chemical mechanical polish (CMP) planarizing method to provide a nominally planarized surface to a trench isolation region formed from a trench fill dielectric layer formed within the trench. Trench isolation regions nominally co-planar with active semiconductor regions within semiconductor substrates are desirable since they optimize, when subsequently forming patterned layers upon those nominally co-planar regions, the limited depth of focus typically achievable with advanced photoexposure tooling.
When forming within advanced integrated circuits trench isolation regions within isolation trenches, it has become common to employ as trench fill dielectric layers gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods. Silicon oxide layers formed employing such methods are desirable since such silicon oxide layers typically possess the inherently superior gap filling characteristics desirable for trenches of limited dimensions typically encountered in advanced integrated circuit fabrication.
While gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods are thus desirable as trench fill layers within trenches within advanced integrated circuit fabrication, methods through which are formed such gap filling silicon oxide layers are not entirely without problems. Specifically, it is known in the art of integrated circuit fabrication that gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods exhibit a surface sensitivity dependent upon the substrate layers upon which are formed those gap filling silicon oxide layers. In particular, when employing as substrate layers thermally grown silicon oxide layers which are typically employed as isolation trench liner layers within isolation trenches formed within silicon semiconductor substrates, gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods exhibit inhibited formation rates in comparison with otherwise equivalent gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods upon substrate layers other than thermally grown silicon oxide layers. The gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods upon the thermally grown silicon oxide layers also typically exhibit inferior bulk quality (as determined by wet etch rates in dilute hydrofluoric acid) and enhanced surface roughness in comparison with otherwise equivalent gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric thermal chemical vapor deposition (SACVD) methods upon substrate layers other than thermally grown silicon oxide layers. Inhibited formation rates within isolation trenches within semiconductor substrates of gap filling silicon oxide trench fill layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods are undesirable since there is then formed within those isolation trenches gap filling silicon oxide layers which are particularly susceptible to dishing when subsequently planarized employing chemical mechanical polish (CMP) planarizing methods. Similarly, inferior bulk quality of such gap filling silicon oxide trench fill layers is undesirable since inferior bulk quality of such gap filling silicon oxide trench fill layers often compromises the dielectric properties of such gap filling silicon oxide trench fill layers. Finally, enhanced surface roughness of such gap filling silicon oxide trench fill layers is undesirable since enhanced surface roughness of such gap filling silicon oxide trench fill layers often provides gap filling silicon trench fill layers of enhanced porosity.
It is thus towards the goal of forming within advanced integrated circuits gap filling silicon oxide trench fill layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods with enhanced bulk quality and diminished surface roughness, while attenuating a surface sensitivity when forming those gap filling silicon oxide trench fill layers, that the present invention is generally directed.
Methods and materials through which silicon oxide layers may be formed with desirable properties within integrated circuits are known in the art of integrated circuit fabrication. For example, Jang et al., in U.S. Pat. No. 5,536,681, disclose a method for improving the gap filling capabilities of silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods. The method employs a nitrogen plasma treatment upon selected topographic portions of a silicon oxide substrate layer formed employing a plasma enhanced chemical vapor deposition (PECVD) method, upon which silicon oxide substrate layer is formed a gap filling oxide layer formed employing an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method.
Further, Jang et al., in U.S. Pat. No. 5,726,090, disclose a method for enhancing gap filling characteristics of ozone assisted sub-atmospheric pressure thermal chemical vapor deposited (SACVD) silicon oxide dielectric layers formed upon thermal silicon oxide trench liner layers within semiconductor substrates within semiconductor integrated circuit microelectronics fabrications. The method employs an intermediate silicon oxide trench liner layer formed upon the thermal silicon oxide trench liner layer prior to forming the ozone assisted sub-atmospheric pressure thermal chemical vapor deposited (SACVD) silicon oxide dielectric layer over the thermal silicon oxide trench liner layer, where the intermediate silicon oxide trench liner layer is treated with a nitrogen plasma prior to forming the ozone assisted sub-atmospheric pressure thermal chemical vapor deposited (SACVD) silicon oxide dielectric layer thereupon.
Finally, Jang et al., in U.S. Pat. No. 5,731,241, disclose a method for protecting a trench fill silicon oxide layer from excessive etching during multiple etching steps. The method employs forming a conformal silicon oxide layer employing sub-atmospheric pressure chemical vapor deposition (SACVD) upon a silicon oxide trench fill layer within a trench within a silicon substrate, wherein the conformal silicon oxide layer has a greater differential etch rate over the trench fill region and functions as a sacrificial layer to protect the trench fill silicon oxide.
Desirable in the art are additional methods through which trenches within substrates employed within integrated circuit fabrication may be filled with gap filling silicon oxide trench fill layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods, while: (1) attenuating a surface sensitivity when forming those gap filling silicon oxide trench fill layers; (2) providing gap filling silicon oxide trench fill layers with enhanced bulk quality (as determined, for example, employing etch rates in dilute hydrofluoric acid); and (3) providing gap filling silicon oxide trench fill layers with diminished surface roughness. Particularly desirable in the art are additional methods through which isolation trenches within semiconductor substrates employed within integrated circuit fabrication may be filled with gap filling silicon oxide trench fill dielectric layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods upon thermal silicon oxide trench liner layers within isolation trenches within silicon semiconductor substrates within semiconductor integrated circuits within microelectronics fabrications in accord with the foregoing three objects. It is towards these goals that the present invention is generally and more specifically directed.